Circuit Reliability Analysis Using Symbolic Techniques

Due to the shrinking of feature size and the significant reduction in noise margins, nanoscale circuits have become more susceptible to manufacturing defects, noise-related transient faults, and interference from radiation. Traditionally, soft errors have been a much greater concern in memories than in logic circuits. However, as technology continues to scale, logic circuits are becoming more susceptible to soft errors than memories. To estimate the susceptibility to errors in combinational logic, the use of binary decision diagrams (BDDs) and algebraic decision diagrams (ADDs) for the unified symbolic analysis of circuit reliability is proposed. A framework that uses BDDs and ADDs and enables the analysis of combinational circuit reliability from different aspects, e.g., output susceptibility to error, influence of individual gates on individual outputs and overall circuit reliability, and the dependence of circuit reliability on glitch duration, amplitude, and input patterns, is presented. This is demonstrated by the set of experimental results, which show that the mean output error susceptibility can vary from less then 0.1% for large circuits and short glitches (20% cycle time) to about 30% for very small circuits and long enough glitches (50% cycle time)