Title :
Open-loop full-digital duty cycle correction circuit
Author :
Yoo, C. ; Jeong, C. ; Kih, J.
Author_Institution :
Dept. of Electron. & Comput. Eng., Hanyang Univ., Seoul, South Korea
fDate :
5/26/2005 12:00:00 AM
Abstract :
The duty cycle of the clock is corrected to be 50% by an open-loop full-digital duty cycle correction (DCC) circuit. Due to its open-loop and full-digital architecture, the DCC completes its operation in less than five clock cycles and can be turned off during power-down state without any concern about losing its information. The DCC has been implemented in a 0.35 μm CMOS process and the measured accuracy is ±0.8% for ±10% input clock duty error.
Keywords :
CMOS digital integrated circuits; clocks; pulse width modulation; 0.35 micron; CMOS process; clock duty error; duty cycle correction circuit; full-digital circuit; open-loop circuit;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20050776
