Aging analysis of nMOS of a 1.3-μm partially depleted SIMOX SOI technology comparison with a 1.3-μm bulk technology

Author

Reimbold, Gilles ; Auberton-Hervé, André-Jacques

Author_Institution

LETI-MSC, CENG, Grenoble, France

Volume

40

Issue

2

fYear

1993

fDate

2/1/1993 12:00:00 AM

Firstpage

364

Lastpage

370

Abstract

Hot carrier degradation of nMOS of a 1.3-μm partially depleted rad-hard SOI CMOS technology is analyzed in detail. The relative importances of the maximum electric field, the localization of the trapped charges, and the LDD structure are pointed out through two-dimensional simulations and systematic comparisons with a 1.3-μm CMOS bulk technology. It is shown that the higher degradation rate of the SOI technology logically results from the contradictory constraints between rad-hardness (low-temperature process) and hot carrier resistance requirements. An annealing scheme comparable to the bulk one would lead to similar degradations

Keywords

CMOS integrated circuits; SIMOX; ageing; annealing; hot carriers; insulated gate field effect transistors; integrated circuit technology; semiconductor device testing; 1.3 micron; LDD structure; LOCOS isolated n-channel MOSFET; annealing scheme; hot carrier degradation; maximum electric field; nMOS aging analysis; partially depleted SIMOX SOI technology; radiation hard SOI CMOS technology; trapped charge localization; two-dimensional simulations; Aging; CMOS technology; Circuit optimization; Doping profiles; Etching; Ionization; MOS devices; Semiconductor films; Stress; Temperature;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.182515

Filename

182515