Minimization of transistor delay at a given power density

Procedures are presented for delay minimization at a given power density in bipolar transistors (BTs) and field-effect transistors (FETs) and used to derive their scaling properties. In BTs minimization is achieved by choosing layer thicknesses that minimize the sum of capacitive and transit delays. Current density is limited at a given stripe width by lateral voltage drops due to base resistance, and this establishes a width-delay relationship. In FETs optimization is achieved by choosing the gate thickness and operating voltage that give minimum delay at a given power density. This leads to scaling rules that include constant-field theory as an approximation, but are more generally applicable. Device-level constraints on power density lead to delay limits in BTs and FETs that scale together. External constraints that are more severe result in delay limits that reduce rapidly with stripe width for FETs but are constant for BTs