Title :
A 1-GS/s 11-bit ADC With 55-dB SNDR, 250-mW Power Realized by a High Bandwidth Scalable Time-Interleaved Architecture
Author :
Gupta, Sandeep K. ; Inerfield, Michael A. ; Wang, Jingbo
Author_Institution :
Teranetics Inc., Santa Clara, CA
Abstract :
A time-interleaved ADC architecture that eliminates the need to correct timing offsets and is yet scalable to high sampling rates is presented. To eliminate timing skews, a Nyquist rate sampling switch is used, which is followed by subsampled, double-sampled time-interleaved sample-and-hold (S/H) stages. This circuit is configured with a special clocking scheme that reduces the loading of the interleaved S/Hs on the Nyquist rate sampling switch, making this scalable to high sampling rates. The subsampled ADCs (sub-ADCs) in this design use a 3.5-bit/stage pipelined architecture. This 1-GS/s 11-bit ADC achieves 55-dB peak SNDR, 58.6-dB SNR, consumes 250-mW core power, and occupies a core area of 3.5 mm2. This circuit is implemented in a dual-gate 1.2 V/2.5 V, 0.13-mum logic CMOS process
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; clocks; sample and hold circuits; signal sampling; 0.13 micron; 1.2 V; 11 bit; 2.5 V; 250 mW; CMOS logic process; Nyquist rate sampling switch; analog-to-digital conversion; phase skew correction; pipeline ADC; special clocking scheme; subsampled ADC; switched-capacitor circuits; time-interleaved ADC; time-interleaved sample-and-hold circuit; Bandwidth; CMOS logic circuits; Clocks; Frequency; Jitter; Quantization; Sampling methods; Signal to noise ratio; Switches; Timing; Analog-to-digital conversion; ENOB; double-sampling; figure of merit (FOM); high-accuracy ADC; high-speed ADC; offset and gain error; phase skew correction; pipeline ADC; sampling networks; switched-capacitor circuits; time-interleaving; timing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2006.884331
