DocumentCode
829275
Title
A 9.95–11.3-Gb/s XFP Transceiver in 0.13- 
CMOS
Author
Kenney, John G. ; Dalton, Declan ; Evans, Eric ; Eskiyerli, Murat Hayri ; Hilton, Barry ; Hitchcox, Dave ; Kwok, Terence ; Mulcahy, Daniel ; McQuilkin, Chris ; Reddy, ViswaBharath ; Selvanayagam, Siva ; Shepherd, Paul ; Titus, Ward S. ; DeVito, Lawrence
Author_Institution
Analog Devices Inc, Somerset, NJ
Volume
41
Issue
12
fYear
2006
Firstpage
2901
Lastpage
2910
Abstract
A 9.95-11.3-Gb/s transceiver in 0.13-mum CMOS for XFP modules is presented. The CDR uses a dual-loop DLL/PLL with a binary phase detector to exceed XFP jitter specifications. The dual loop solves the problem of having a controlled jitter transfer bandwidth with a binary phase detector. A half rate binary phase detector with a 2:1 serializer implements full-rate I/O. Dispersion jitter from 12´´ of FR4 is equalized resulting in system JGEN under 4 mUIRMS and 35 mUI PP. Power consumption is 800 mW
Keywords
delay lock loops; frequency locked loops; phase locked loops; synchronisation; transceivers; 0.13 micron; 800 mW; XFP jitter; XFP transceiver; binary phase detector; clock and data recovery; delay-locked loop; dual-loop DLL/PLL; frequency-locked loop; phase-locked loop; Bandwidth; Delay; Detectors; Frequency locked loops; Jitter; Phase detection; Phase locked loops; SONET; Transceivers; Voltage-controlled oscillators; Clock and data recovery (CDR); delay-locked loop (DLL); frequency-locked loop (FLL); phase-locked loop (PLL); transceiver;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.2006.884344
Filename
4014616
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