DocumentCode :
829364
Title :
A 1-ps Resolution Jitter-Measurement Macro Using Interpolated Jitter Oversampling
Author :
Nose, Koichi ; Kajita, Mikihiro ; Mizuno, Masayuki
Author_Institution :
NEC Corp., Kanagawa
Volume :
41
Issue :
12
fYear :
2006
Firstpage :
2911
Lastpage :
2920
Abstract :
This paper reports the development of an in-field real-time successive jitter-measurement macro whose features include 1-ps resolution jitter measurement. The newly developed jitter-measurement macro has four key features: 1) interpolated jitter oversampling; 2) a hierarchical Vernier delay line; and 3)feedforward calibration, each of which helps attain high jitter-measurement resolution; as well as 4) an oversampling rate and measurement range-control technique. A test chip of the macro has been fabricated in a 90-nm process. It successfully measures small random jitter with 1-ps resolution, and large deterministic jitter can also be measured by extending the jitter-measurement range by a factor of 4
Keywords :
delay lines; integrated circuit measurement; jitter; sampling methods; 90 nm; feedforward calibration; hierarchical Vernier delay line; integrated circuit measurement; interpolated jitter oversampling; jitter-measurement macro; measurement range-control technique; oversampling rate; Attenuation measurement; Clocks; Histograms; Integrated circuit measurements; Large scale integration; Measurement errors; Noise measurement; Nose; Semiconductor device measurement; Timing jitter; Calibration; integrated circuit measurement; jitter measurement; oversampling;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.2006.884402
Filename :
4014625
Link To Document :
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