DocumentCode :
829414
Title :
A 5-GHz 108-Mb/s 2 \\times 2 MIMO Transceiver RFIC With Fully Integrated 20.5-dBm {\\rm P}_{\\rm 1dB}
Author :
Palaskas, Yorgos ; Ravi, Ashoke ; Pellerano, Stefano ; Carlton, Brent R. ; Elmala, Mostafa A. ; Bishop, Ralph ; Banerjee, Gaurab ; Nicholls, Rich B. ; Ling, Stanley K. ; Dinur, Nati ; Taylor, Stewart S. ; Soumyanath, K.
Author_Institution :
Intel Corp., Hillsboro, OR
Volume :
41
Issue :
12
fYear :
2006
Firstpage :
2746
Lastpage :
2756
Abstract :
Multiple antenna transceivers combined with MIMO signal processing offer the potential for increased data rates and/or range in wireless systems. This paper presents a fully integrated 5-GHz 2times2 MIMO WLAN transceiver RFIC implemented in 90-nm CMOS. The paper identifies the key MIMO integration issues and proposes techniques to optimize MIMO performance. It is shown that crosstalk between the multiple transceivers residing on the same die can degrade MIMO performance and has to be carefully minimized, especially when power amplifiers are integrated on-die. A shared LO generation and distribution network is designed to maximize MIMO phase noise immunity without introducing undesired crosstalk. The fabricated MIMO receiver achieves a sensitivity of -63 dBm while receiving 108Mb/s in MIMO spatial multiplexing mode in the presence of a 25-ns Rayleigh fading channel. The sensitivity of a single receiver in the presence of AWGN noise is -76 dBm. Linearized 3.3-V 5-GHz power amplifiers with P1dB=20.5<!-- Character "" changed to --> dBm deliver an average power of +13/+16 dBm each, in MIMO/SISO modes respectively (EVM=-27/-25 dB). The measured performance demonstrates the effectiveness of the isolation techniques employed. The system in a package includes an 18 mm2 die and microstrip front-end matching networks implemented on a flip-chip package
Keywords :
CMOS integrated circuits; MIMO communication; Rayleigh channels; crosstalk; flip-chip devices; microwave power amplifiers; phase noise; radiofrequency integrated circuits; system-in-package; transceivers; wireless LAN; 108 Mbit/s; 25 ns; 3.3 V; 5 GHz; 90 nm; AWGN noise; CMOS integrated circuits; LO generation; MIMO receiver; MIMO signal processing; MIMO transceiver RFIC; MIMO/SISO modes; Rayleigh fading channel; WLAN transceiver; crosstalk; distribution network; flip-chip package; microstrip front-end matching networks; multiple antenna transceivers; phase noise immunity; power amplifiers; radiofrequency integrated circuit; spatial multiplexing mode; wireless LAN; wireless systems; Crosstalk; Degradation; MIMO; Packaging; Phase noise; Power amplifiers; Radiofrequency integrated circuits; Signal processing; Transceivers; Wireless LAN; Crosstalk; MIMO; RFIC; spatial multiplexing; wireless LAN (WLAN);
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.2006.884795
Filename :
4014629
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