Simulation of Migration Effects in Solder Bumps

Due to miniaturization, the width of interconnects, as well as the dimensions of solder bumps, decreases. As a result of the finer pitch, the density of solder bumps in flip-chip designs increases. This allows the usage of small 3-D assembly technologies like package-on-package in compact applications. The reduction of the geometrical dimensions leads to an increase of the carried current density in the solder bumps. Due to the device design rules, the current flowing through such a solder bump in flip-chip designs extends, for instance, from 0.2 to 0.4 A. The geometry of the solder bump and the trace leads to current density distributions with high local concentrations, which are known as current crowding (CC). CC is occurring at the contact between the trace and the solder bump, as well as in discontinuities of the traces like vias, etc. Due to CC migration, effects like electro- and thermomigration become critical reliability problems in such assembly technologies [3], [4], [19], [20]. Under high dc current density conditions, electromigration in the solder joint is known as a reliability concern for high-density flip-chip packaging and power packaging [8]. This paper will give an overview of thermal-electrical and mechanical finite-element simulations of migration effects in solder bumps and related assembly technologies. The effects will be illustrated by some simulation examples.