Title :
Wide-Range 5.0/3.3/1.8-V I/O Buffer Using 0.35-m 3.3-V CMOS Technology
Author :
Lee, Tzung-Je ; Chang, Tieh-Yen ; Wang, Chua-Chin
Author_Institution :
Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung
fDate :
4/1/2009 12:00:00 AM
Abstract :
A 5.0/3.3/1.8-V tolerant I/O buffer implemented using typical CMOS 2P4M 0.35-mum process is proposed in this paper. Unlike traditional mixed-voltage-tolerant I/O buffers, the proposed I/O buffer can transmit and receive signals with voltage levels of 5.0/3.3/1.8 V. By using a stacked PMOS and a stacked NMOS at the output stage and a dynamic gate bias generator providing appropriate control voltages for the gates of the stacked PMOS, gate-oxide overstress and hot-carrier degradation are avoided. Moreover, gate-tracking and floating n-well circuits are used to remove undesirable leakage current paths. The proposed topology can be applied to any technologies with the constraint of VDD < VDDH < 2 times, which should be considered carefully in sub-100-nm technologies. Measurement results on silicon verify the function and the gate-oxide reliability of the proposed I/O buffer. The maximum transmitting speed of the proposed I/O buffer is measured to be 80/120/84 Mb/s for the supply voltage of I/O buffer at 5.0/3.3/1.8 V, respectively, given the load of 29 pF.
Keywords :
CMOS integrated circuits; buffer circuits; circuit reliability; CMOS technology; bit rate 120 Mbit/s; bit rate 80 Mbit/s; bit rate 84 Mbit/s; capacitance 29 pF; dynamic gate bias generator; floating n-well circuits; gate-oxide overstress; gate-oxide reliability; gate-tracking; hot-carrier degradation; mixed-voltage-tolerant I/O buffers; size 0.35 mum; stacked NMOS; stacked PMOS; voltage 1.8 V; voltage 3.3 V; voltage 5.0 V; voltage control; Floating n-well; I/O buffer; fully mixed-voltage-tolerant; gate-tracking; level converter;
Journal_Title :
Circuits and Systems I: Regular Papers, IEEE Transactions on
DOI :
10.1109/TCSI.2008.2002921