Abstract :
Wave pipelining offers faster clock rates than conventional pipelining; however, wave-pipelined circuit design is time-consuming and requires a high level of expertise. Wave pipelining is especially vulnerable to delay changes due to variations in process, voltage, and temperature (PVT) and in the operating environment. Wave pipelining´s performance is also affected by the minimum-delay path. Thus, minimum delay is also a concern for wave-pipelined circuits. Automating wave-pipelined circuit design, especially generating a design netlist, is therefore challenging. To automate the generation of wave-pipelined design netlists, we use a commercial synthesis tool, the synopsys design compiler, and delay-balancing scripts.
Keywords :
CMOS logic circuits; circuit CAD; integrated circuit design; delay-balancing scripts; minimum delay path; synopsys design compiler; synthesis tool; wave pipelining; wave-pipelined circuit design automation; wave-pipelined design netlists; Adders; Automatic control; CMOS logic circuits; Circuit synthesis; Clocks; Delay; Engines; Logic design; Pipeline processing; Sun;
