• DocumentCode
    830331
  • Title

    How much variability can designers tolerate?

  • Author

    Kahng, Andrew B.

  • Author_Institution
    Comput. Sci. & Eng. Dept., California Univ., San Diego, CA, USA
  • Volume
    20
  • Issue
    6
  • fYear
    2003
  • Firstpage
    96
  • Lastpage
    97
  • Abstract
    Designers hate large variations in a gate´s critical dimensions (CDs) because large variations imply large guardbanding in design. Lithographers hate small variations in CD numbers because they imply impossible process windows. With the publication of the 2003 International Technology Roadmap for Semiconductors (1TRS), gate CD control requirements for lithography and front-end (etching) processes will doubtless receive intense scrutiny.
  • Keywords
    etching; integrated circuit design; lithography; logic gates; CD; ITRS; International Technology Roadmap for Semiconductors; front-end process; gate critical dimensions; integrated circuit design; lithography; Companies; Control systems; Counting circuits; Electronic design automation and methodology; Isolation technology; Lenses; Logic; Process design; Semiconductor device modeling; Testing;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/MDT.2003.1246168
  • Filename
    1246168
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=830331