• DocumentCode
    830681
  • Title

    Systolic realisation for 1-D circular convolution using the Chinese remainder theorem

  • Author

    Wang, Lingfeng ; Hartimo, I.

  • Author_Institution
    Helsinki Univ. of Technol., Espoo, Finland
  • Volume
    29
  • Issue
    2
  • fYear
    1993
  • Firstpage
    165
  • Lastpage
    166
  • Abstract
    A novel systolic array is proposed for efficient implementation of one-dimensional circular convolution (CC). The array performs the Chinese remainder theorem to avoid the need for broadcasting inputs to all cells and circular communication between the cells. The entire hardware is connected in a full pipeline with O(2N) throughput.
  • Keywords
    VLSI; digital signal processing chips; pipeline processing; systolic arrays; Chinese remainder theorem; O(2N) throughput; VLSI array; digital signal processing; one-dimensional circular convolution; pipelined architecture; systolic array;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19930111
  • Filename
    184560