DocumentCode :
831920
Title :
Redundancy removal for sequential circuits without reset states
Author :
Cheng, Kwang-Ting
Author_Institution :
AT&T Bell Labs., Murray Hill, NJ, USA
Volume :
12
Issue :
1
fYear :
1993
fDate :
1/1/1993 12:00:00 AM
Firstpage :
13
Lastpage :
24
Abstract :
Methods for identifying and removing redundancy in synchronous sequential circuits that do not have a global reset state are proposed. All existing structure-level test generators use three-valued logic, which is not completely accurate, to process circuits that have an unknown initial state. A fault that is reported undetectable by such test generators is not necessarily redundant. It is shown that if a fault is potentially undetectable (p-undetectable), it is redundant. An algorithm that identifies p-undetectable faults is described. For large circuits, a practical procedure for removing redundancy in the feedback-free portion of the circuits is given. An alternative approach to identifying redundancy that does not require determining the potential detectability of faults is also presented. Derivations of conditions in which undetectable faults are redundant are provided. Algorithms for identifying unactivatable and unpropagable faults are described. These algorithms are implemented and incorporated in the redundancy removal system MIRACLE
Keywords :
fault location; logic testing; redundancy; sequential circuits; MIRACLE; fault identification algorithm; feedback-free portion; p-undetectable faults; redundancy removal; synchronous sequential circuits; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Fault diagnosis; Feedback circuits; Logic circuits; Logic testing; Redundancy; Sequential circuits;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.184840
Filename :
184840
Link To Document :
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