• DocumentCode
    831954
  • Title

    Formal definitions of edge-based geometric design rules

  • Author

    Jeppson, Kjell O. ; Christensson, Sven ; Hedenstierna, Nils

  • Author_Institution
    Dept. of Solid-State Electron., Chalmers Univ. of Technol., Goteborg, Sweden
  • Volume
    12
  • Issue
    1
  • fYear
    1993
  • fDate
    1/1/1993 12:00:00 AM
  • Firstpage
    59
  • Lastpage
    69
  • Abstract
    A structured method for geometric design rule definitions is presented in terms of edge-based constraints. Using this approach, intralayer design rules such as width and spacing of single layers, and interlayer design rules such as clearance, margin, extension, and overlap of two different layers can be specified in terms of two high-level design rule macros only. The tedious and complicated task of specifying detailed design rules in the technology file is thereby eliminated and placed by a simple macro rule file giving a much better overview of the design rules. Efficient rule compilers have been developed to expand these macro descriptions of the design rules onto basic checks for Magic and for corner-based design rule checking. As an example, the MOSIS scalable CMOS design rule set can be described in terms of the two design rule macros only. More complicated design rules, such as conditional and conjunctive design rules, are also discussed
  • Keywords
    VLSI; circuit layout CAD; integrated circuit technology; IC layout; MOSIS scalable CMOS design; Magic; VLSI layout; conditional design rules; conjunctive design rules; corner-based design rule checking; design rule definitions; edge-based geometric design rules; high-level design rule macros; interlayer design rules; intralayer design rules; macro rule file; rule compilers; Computer aided manufacturing; Design automation; Design methodology; Fabrication; Integrated circuit layout; Integrated circuit yield; Manufacturing processes; Process design; Production; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.184843
  • Filename
    184843