A proposed method for determining a MOSFET gate electrode´s bottom dimension and the on-state fringing capacitance

A novel electrical method is proposed for determining two of the most important MOSFET device performance parameters, the physical dimension of the gate electrode at the gate oxide interface (bottom dimension) and the on-state (substrate in inversion) fringing capacitance of the gate. For characterization, the method requires simple capacitors, fabricated using identical processing steps that affect the dimensions of a MOSFET gate electrode. The required data are quasi-static C-V measurements at two or more biases. The physical basis and potential accuracy of this characterization method have been verified, based on detailed two-dimensional numerical device simulation. This method potentially can be applied to monitor process variations and to studies of the cause-effect relation between processes and device performance. In addition, the accurate determination of these parameters from device wafers is fundamentally required for calibrating physically based two-dimensional process and device simulators, and improving their predictive capability