Distributed double-phase switch

A packet switch architecture is proposed for the broadband ISDN. It is in three stages. The first stage consists of simple distributors which transfer the incoming packets to the later stages regularly and in balance. The next two stages carry out the routing; they are composed of small knockout switches. The authors model the switching system as an M/D/m queuing model and show that, when the load is under 0.84, the following features are provided in a service-independent communication: the probability of losing a packet is less than 10 ^-6; and the average delay of packets is less than three packet time. The switching system can offer higher load in a service dependent communication while maintaining the same transmission quality. They evaluate the cost and throughput of the design in terms of today´s VLSI technologies. For a typical local switch centre whose size is less than 16384*16384, the cost is 2 chips per port and a line rate of 150 Mbit/s is achievable.<>