Abstract :
Radical changes are in the offing for transistors as their dimensions shrink to a few tens of nanometers. In 10 years time, the gate length-the market for gauging how small the transistor is-will be roughly one-fifth the size of the smallest in production today, only 10 nm instead of today´s 50 nm. To get to that size and ensure that the transistor still operates will require many changes: to improve performance, silicon will be mixed with a semiconductor like germanium to produce a more spacious, strained crystalline structure that lets electric charge carriers move faster; to reduce the leakage of current that drives up power consumption, gate oxides will be made of materials with more than eight times the dielectric constant (k) of today´s silicon dioxide; for better control of the transistor´s on and off states, gates will be of metal, instead of polysilicon; and for better control and (again) to reduce power consumption, gates themselves will be doubled up so that two will do the job a single gate does now. Among these techniques, strained silicon is the only one to have been commercialized so far. The rest are still at various stages of R&D.
Keywords :
CMOS integrated circuits; ULSI; VLSI; field effect transistors; integrated circuit design; integrated circuit technology; nanotechnology; 10 nm; FinFET; current leakage reduction; dielectric constant; electric charge carriers velocity improvement; gate oxides; germanium; metal gates; silicon; strained crystalline structure; transistors; Charge carriers; Crystalline materials; Crystallization; Energy consumption; Germanium; Production; Silicon; Size control; Strain control; Transistors;