Title :
48 Gbit/s InP DHBT MS-DFF with very low time jitter
Author :
Konczykowska, A. ; Jorge, E. ; Kasbari, A. ; Sahri, N. ; Godin, J.
Author_Institution :
OPTO+, Alcatel R&I, Marcoussis, France
fDate :
9/12/2002 12:00:00 AM
Abstract :
A master-slave D-type flip-flop (MS DFF) fabricated in a self-aligned InP DHBT technology is presented. The packaged circuit shows full-rate clock operation at 48 Gbit/s. Very low time jitter and good retiming capabilities are observed. Layout aspects, packaging and measurement issues are discussed in particular
Keywords :
III-V semiconductors; bipolar logic circuits; flip-flops; heterojunction bipolar transistors; high-speed integrated circuits; indium compounds; integrated circuit layout; integrated circuit packaging; timing jitter; 48 Gbit/s; DHBT MS-DFF; InP; InP DHBT technology; layout aspects; low time jitter; master-slave D-type flip-flop; packaged circuit; retiming capabilities; self-aligned DHBT technology;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20020777
