DocumentCode :
83322
Title :
Identifying the First Layer to Fail in Dual-Layer {\\rm SiO}_{\\rm x}/{\\rm HfSiON} Gate Dielectric Stacks
Author :
Padovani, A. ; Raghavan, N. ; Larcher, Luca ; Kin Leong Pey
Author_Institution :
Dipt. di Sci. e Metodi dell´Ing., Univ. di Modena e Reggio Emilia, Reggio Emilia, Italy
Volume :
34
Issue :
10
fYear :
2013
fDate :
Oct. 2013
Firstpage :
1289
Lastpage :
1291
Abstract :
We use the thermo-chemical model of bond breakage to investigate the degradation occurring in dual-layer SiOx/HfSiON gate dielectric stacks during low-compliance soft breakdown (BD) experiments, with the ultimate goal of identifying the first layer that degrades. Time-dependent dielectric breakdown experiments reveal that the degradation of conventional SiON and SiOx/HfSiON dielectric stacks have the same kinetics, i.e., activation energy and field acceleration factor. This finding, supported by physics-based BD simulations, shows that the degradation in SiOx/HFSiON stacks is governed by the defect generation in the silicon oxide interfacial layer, which is the first that degrades in the multilayer stack.
Keywords :
electric breakdown; hafnium compounds; silicon compounds; SiOx-HfSiON; activation energy; bond breakage; defect generation; dielectric breakdown; dual-layer gate dielectric stacks; field acceleration factor; multilayer stack; physics-based BD simulations; silicon oxide interfacial layer; soft breakdown experiments; thermo-chemical model; Degradation; Dielectric breakdown; Dielectrics; Logic gates; Silicon; Stress; High-$k$ dielectric stacks; interfacial layer; reliability; soft breakdown; thermo-chemical model; time-dependent dielectric breakdown (TDDB);
fLanguage :
English
Journal_Title :
Electron Device Letters, IEEE
Publisher :
ieee
ISSN :
0741-3106
Type :
jour
DOI :
10.1109/LED.2013.2275182
Filename :
6579645
Link To Document :
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