An analog front end for full-duplex digital transceivers working on twisted pairs

Author

Agazzi, Oscar ; Adan, Alberto A.

Author_Institution

Harris Semicond. Corp., Melbourne, FL, USA

Volume

24

Issue

2

fYear

1989

fDate

4/1/1989 12:00:00 AM

Firstpage

229

Lastpage

240

Abstract

An analog front-end chip fabricated in a 4- mu m CMOS process has been described. The chip, together with a digital signal processor, implements a full-duplex transceiver for twisted pairs. A fully differential architecture has been used in all the analog signal-processing blocks to get high dynamic range and common-mode noise rejection. The front-end output is a 12-b word generated by a 6- mu s A/D (analog-to-digital) converter with autocalibration, with a linearity better than 1 LSB.<>

Keywords

CMOS integrated circuits; ISDN; analogue-digital conversion; data communication equipment; linear integrated circuits; transceivers; 4 micron; 6 mus; ADC; CMOS; ISDN; analog front end; analog front-end chip; analog signal-processing blocks; autocalibration; common-mode noise rejection; differential architecture; digital signal processor; front-end output; full-duplex digital transceivers; high dynamic range; linearity; transceiver for twisted pairs; Adaptive equalizers; Delta-sigma modulation; Echo cancellers; ISDN; Low pass filters; Strontium; Timing; Transceivers; Very large scale integration;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.18581

Filename

18581