Algorithm for the generation of SIC pairs and its implementation in a BIST environment

Built-in self test (BIST) techniques provide for on-chip test pattern generation and response verification operations, and therefore constitute an efficient alternative to external testing for the detection of faults appearing in VLSI circuits. Failure mechanisms that commonly appear in high-speed CMOS VLSI circuits cannot be modelled adequately as stuck-at faults. The detection of these faults requires the application of pairs of patterns to the inputs of the circuit under test. Single input change (SIC) pairs are pairs of patterns where the first pattern of each pair differs from the second pattern in exactly one bit. SIC pairs have been proved to be extremely useful for the detection of stuck-open and delay faults. In this paper a novel algorithm for the generation of SIC pairs is presented, termed decoder-based SIC pair generation (DSG) algorithm. An implementation of the DSG algorithm in a BIST environment is also presented. The number of memory elements utilised is the lowest reported in the literature