Title :
An analog PLL-based clock and data recovery circuit with high input jitter tolerance
Author :
Sun, Sam Yinshang
Author_Institution :
Rockwell Int., Newport Beach, CA, USA
fDate :
4/1/1989 12:00:00 AM
Abstract :
A clock and data recovery circuit for a T1 network is described. A fully integrated phase-locked loop (PLL) extracts the carrier signal embedded in the data. Two trimming DACs simultaneously bring the VCO center frequency and the PLL closed-loop bandwidth to their specified values. A triple sampler captures the jittering data and aligns them with the recovered clock. The input jitter of this circuit is three times more than previously reported PLL-based circuits
Keywords :
CMOS integrated circuits; ISDN; phase-locked loops; PLL closed-loop bandwidth; T1 network; VCO center frequency; analog PLL-based clock; carrier signal recovery; clock recovery circuit; data recovery circuit; fully integrated phase-locked loop; high input jitter tolerance; trimming DACs; triple sampler; Bandwidth; Charge pumps; Clocks; Data mining; Frequency; Jitter; Phase detection; Phase locked loops; Tuned circuits; Voltage-controlled oscillators;
Journal_Title :
Solid-State Circuits, IEEE Journal of
