A dynamic programming processor for speech recognition

Author

Quénot, Georges M. ; Gauvain, Jean-Luc ; Gangolf, Jean-Jacques ; Mariani, Joseph J.

Author_Institution

LIMSI-CNRS, Orsay, France

Volume

24

Issue

2

fYear

1989

fDate

4/1/1989 12:00:00 AM

Firstpage

349

Lastpage

357

Abstract

A dynamic programming processor with parallel and pipeline architecture is described. A 2- mu m CMOS technology was applied to the DP processor, which is composed of 127309 transistors on a 7.17*8.62-mm/sup 2/ die and is housed in an 84-pin PLCC (plastic leaded chip carrier) or PGA (pin grid array) package. The clock frequency is 20 MHz, and the instruction cycle time is 100 ns. Precise electrical simulations permitted the safe use of nonstandard logic and area and power reduction. Implementation of a direct access to all internal registers has proven useful for chip test and software development. A system using one DP processor has given very good results on a wide variety of applications and 0.48% error rate on tests with standard NATO tapes. These results are significantly better than those published for other systems on the same tests.<>

Keywords

CMOS integrated circuits; VLSI; microprocessor chips; parallel architectures; pipeline processing; speech analysis and processing; speech recognition; 100 ns; 2 micron; 20 MHz; 8.62 mm; CMOS; DP processor; PGA; PLCC; chip test; clock frequency; direct access to all internal registers; dynamic programming processor; error rate; instruction cycle time; nonstandard logic; pin grid array; pipeline architecture; plastic leaded chip carrier; power reduction; software development; speech recognition; standard NATO tapes; Architecture; CMOS process; CMOS technology; Clocks; Dynamic programming; Electronics packaging; Pipelines; Plastic packaging; Speech recognition; System testing;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.18595

Filename

18595