A 0.8- mu m CMOS technology for high-performance ASIC memory and channelless gate array

Author

Liou, Fu-Tai ; Han, Yu-Pin ; Bryant, Frank R. ; Zamanian, Mehdi

Author_Institution

SGS Thomson Microelectron., Carrollton, TX, USA

Volume

24

Issue

2

fYear

1989

fDate

4/1/1989 12:00:00 AM

Firstpage

380

Lastpage

387

Abstract

A 0.8- mu m polycide-gate, double-layer-metal CMOS technology is described. Nominal device gate lengths down to 0.8 (+or-0.2) mu m are used for both n- and p-channel transistors. Compact isolation, 175-A gate oxide grown in dry/wet/dry ambient, shallow-junction halo-implanted lightly doped drain n and p devices, TiN contact barrier, and a planarized double-layer-metal process are all integrated and demonstrated with a 0.8- mu m full-CMOS 16K SRAM (static random-access memory) circuit. The device process integrity, design margins, performance, reliability, product yield and speed enhancement are all discussed in detail.<>

Keywords

CMOS integrated circuits; application specific integrated circuits; integrated circuit technology; integrated memory circuits; logic arrays; random-access storage; 0.8 micron; 16 kbit; CMOS; SRAM; TiN contact barrier; channelless gate array; design margins; device process integrity; double-layer-metal CMOS technology; gate lengths; gate oxide; halo-implanted lightly doped drain; high-performance ASIC memory; isolation; performance; planarized double-layer-metal process; polycide-gate; product yield; reliability; shallow-junction; speed enhancement; static random-access memory; Application specific integrated circuits; CMOS memory circuits; CMOS technology; Etching; Integrated circuit reliability; Isolation technology; Oxidation; Random access memory; Space technology; Tin;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.18598

Filename

18598