Boolean decomposition in multilevel logic optimization

Author

Devadas, Srinivas ; Wang, Albert R. ; Newton, A. Richard ; Sangiovanni-Vincentelli, Alberto

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA

Volume

24

Issue

2

fYear

1989

fDate

4/1/1989 12:00:00 AM

Firstpage

399

Lastpage

408

Abstract

Algorithms are presented for Boolean decomposition, which can be used to decompose a programmable logic array (PLA) into a set of smaller interconnected PLAs such that the overall area of the resulting logic network, deemed to be the sum of the areas of the constituent PLAs, is minimized. These algorithms can also be used to identify good Boolean factors which can be used as strong divisors during the logic optimization to reduce the literal counts/area of general multilevel logic networks. Excellent results have been obtained.<>

Keywords

Boolean algebra; logic arrays; many-valued logics; Boolean decomposition; Boolean factors; PLA; area minimisation; logic optimization; multilevel logic networks; multilevel logic optimization; programmable logic array; set of smaller interconnected PLAs; Boolean functions; Design optimization; Encoding; Equations; Integrated circuit interconnections; Logic arrays; Logic functions; Minimization; Network synthesis; Programmable logic arrays;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.18601

Filename

18601