Title :
SPIM: a pipelined 64*64-bit iterative multiplier
Author :
Santoro, Mark R. ; Horowitz, Mark A.
Author_Institution :
Center for Integrated Syst., Stanford Univ., CA, USA
fDate :
4/1/1989 12:00:00 AM
Abstract :
A 64*64-bit iterating multiplier, the Stanford pipelined iterative multiplier (SPIM), is presented. The pipelined array consists of a small tree of 4:2 adders. The 4:2 tree is better suited than a Wallace tree for a VLSI implementation because it is a more regular structure. A 4:2 carry-save accumulator at the bottom of the array is used to iteratively accumulate partial products, allowing a partial array to be used, which reduces area. SPIM was fabricated in a 1.6- mu m CMOS process. It has a core size of 3.8 mm*6.5 mm and contains 41000 transistors. The on-chip clock generator runs at an internal clock frequency of 85 MHz. The latency for a 64*64-bit fractional multiply is under 120 ns, with a pipeline rate of one multiply every 47 ns.<>
Keywords :
CMOS integrated circuits; VLSI; digital arithmetic; integrated logic circuits; multiplying circuits; pipeline processing; 1.6 micron; 120 ns; 47 ns; 4:2 carry-save accumulator; 85 MHz; CMOS process; SPIM; Stanford pipelined iterative multiplier; VLSI implementation; adder tree; digital IC; internal clock frequency; logic circuits; on-chip clock generator; partial array; pipelined array; CMOS process; Clocks; Delay; Frequency; Hardware; Out of order; Pipeline processing; Silicon; Very large scale integration;
Journal_Title :
Solid-State Circuits, IEEE Journal of
