Title :
Simple optimising methodology for static frequency divider design
Author :
Dong, P. ; Hayes-Gill, B. ; Harrison, I.
Author_Institution :
Sch. of Electr. & Electron. Eng., Univ. of Nottingham
Abstract :
An optimising method to improve the speed of a source-coupled-logic static frequency divider is presented. A piecewise linear transistor model is applied to simplify the large-signal analysis. The optimised circuit parameters can be quickly estimated from the analysis result. The simulation and measurement results on a 0.35 mum CMOS process have been used to demonstrate this optimisation method
Keywords :
CMOS logic circuits; circuit optimisation; frequency dividers; piecewise linear techniques; 0.35 micron; CMOS process; large-signal analysis; optimising methodology; piecewise linear transistor model; source-coupled-logic; static frequency divider;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20062346
