Title :
Surface Passivation of Ge MOS Devices by
With Sub-nm EOT
Author :
Chia-Chun Lin ; Yung-Hsien Wu ; Chao-Yi Wu ; Ching-Wei Lee
Author_Institution :
Dept. of Eng. & Syst. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Abstract :
Ge MOS devices passivated by SmGeOx with equivalent oxide thickness of 0.61 nm were employed as the platform to evaluate the eligibility of SmGeOx as Ge surface passivation layer. The SmGeOx layer was formed by deposition of Sm2O3 on Ge substrate with a subsequent O2 annealing and the formation of SmGeOx was confirmed by X-ray photoelectron spectroscopy. The tiny frequency dispersion in capacitance measurement and a low interface trap density of 5.1×1011 cm-2eV-1 near midgap attest to desirable passivation effect and it can be ascribed to Sm-Ge-O bonding, which is favorable in mitigating dangling bonds at Ge surface. In addition, the small hysteresis in capacitance also suggests good quality of bulk dielectric. Due to the small amount of bulk traps and large conduction band offset with respect to Ge, it enjoys low leakage current of 0.36 A/cm2 at gate bias of Vfb (flatband voltage)-1 V. Through the test of bias temperature instability, the passivation layer demonstrates reasonable reliability performance in terms of 65-mV flatband voltage shift at 85 °C after stressing with -16 MV/cm for 1000 s. With these characteristics, SmGeOx is promising as a passivation layer for aggressively scaled Ge MOS devices.
Keywords :
MIS devices; X-ray photoelectron spectra; annealing; capacitance measurement; conduction bands; dielectric materials; elemental semiconductors; germanium; interface states; leakage currents; passivation; samarium compounds; semiconductor device reliability; Ge; Ge MOS devices; Ge substrate; Sm-Ge-O bonding; SmGeOx; X-ray photoelectron spectroscopy; annealing; bias temperature instability; bulk dielectric; capacitance measurement; conduction band offset; equivalent oxide thickness; frequency dispersion; interface trap density; leakage current; reliability; size 0.61 nm; sub-nm EOT; surface passivation; temperature 85 degC; voltage 65 mV; Annealing; Dielectrics; Leakage currents; Logic gates; MOS devices; Passivation; Performance evaluation; ${rm SmGeO}_{x}$ ; EOT; Ge surface passivation; bias temperature instability; interface trap density; leakage current;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2014.2298871