Title :
A VLSI processor for parallel contour tracing
Author :
Agi, Iskender ; Hurst, Paul J. ; Jain, Anil K.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Davis, CA, USA
fDate :
2/1/1992 12:00:00 AM
Abstract :
A custom IC processor that traces contours in black-and-white images is described. The CMOS IC contains a finite state machine, an arithmetic logic unit (ALU), an input delay line, and RAM. Each process extracts the edges from a rectangular portion of the input image and traces the edges, producing a description of the contours. A complete tracing system employs an array of these processors. The array architecture allows expansion to handle arbitrarily large images. The processors trace independently, thereby providing fully parallel high-speed operation. Partial contours are generated as a result of the partitioning of the image among the processors. A postprocessor links any partial contours created by the subdivision of the input image. The contour-tracing algorithm and simulation results for compression ratio and number of operations are presented. The architecture and measured performance of the IC are described
Keywords :
CMOS integrated circuits; VLSI; application specific integrated circuits; computerised pattern recognition; computerised picture processing; digital signal processing chips; parallel architectures; CMOS IC; RAM; VLSI processor; arithmetic logic unit; array architecture; black-and-white images; compression ratio; contour tracing; custom IC; finite state machine; input delay line; parallel high-speed operation; partial contours; pattern recognition; Automata; Biomedical measurements; CMOS integrated circuits; Delay lines; Helium; Partitioning algorithms; Pixel; Read-write memory; Signal processing algorithms; Very large scale integration;
Journal_Title :
Signal Processing, IEEE Transactions on