DocumentCode :
835113
Title :
Hardness Assurance Guidelines for Moderate Neutron Environment Effects in Bipolar Transistors and Integrated Circuits
Author :
Berger, Robert A. ; Azarewicz, Joseph L. ; Eisen, Harvey
Author_Institution :
IRT Corporation, P.O. Box 80817, San Diego, CA 92138
Volume :
25
Issue :
6
fYear :
1978
Firstpage :
1555
Lastpage :
1560
Abstract :
This paper sets forth procedures which provide effective means of obtaining semiconductor devices whose neutron-induced response is within known, acceptable limits. These Hardness Assurance (HA) procedures can be applied to bipolar transistors, TTL (54/74 series) digital integrated circuits, and operational amplifiers (such as the 741). HA is implemented by imposing two control levels on the supplier and/or two quality levels on the user. The supplier controls include process controls, 100% nondegrading screens, and lot sample radiation tests. The user chooses the minimum number of HA controls necessary to obtain a population proportion of 80% or better. The reason for choosing the 80% point is based upon lot sample statistics and a sample size of 10 units. These HA procedures for the supplier and the user, together with a lot sample statistical plan based on one-sided tolerance limit factors and part selection based on a 10x radiation overtest, yield an estimate of minimum lot quality at low test cost.
Keywords :
Bipolar integrated circuits; Bipolar transistors; Circuit testing; Digital integrated circuits; Guidelines; Neutrons; Operational amplifiers; Process control; Proportional control; Semiconductor devices;
fLanguage :
English
Journal_Title :
Nuclear Science, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9499
Type :
jour
DOI :
10.1109/TNS.1978.4329571
Filename :
4329571
Link To Document :
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