Title :
SJ-LDMOS with high breakdown voltage and ultra-low on-resistance
Author :
Chen, W. ; Zhang, B. ; Li, Z.
Author_Institution :
Center of IC Design, Univ. of Electron. Sci. & Technol. of China, Chengdu Sichuan
Abstract :
A new design concept is proposed to eliminate the substrate-assisted depletion effect in a super-junction (SJ) LDMOS. The key feature of the concept is that a non-uniform N-buried layer is implemented which compensates for the charge interaction between the P-substrate and SJ region, realising high breakdown voltage (>700 V) and ultra-low on-resistance. Furthermore, the proposed device is compatible with smart power technology
Keywords :
MOSFET; semiconductor device breakdown; semiconductor device reliability; P-substrate; TV-buried layer; breakdown voltage; smart power technology; substrate-assisted depletion effect; super-junction LDMOS; super-junction region;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20062751
