DocumentCode
83559
Title
Impact of Fermi Level Pinning Due to Interface Traps Inside the Conduction Band on the Inversion-Layer Mobility in
Metal–
Author
Taoka, Noriyuki ; Yokoyama, Masafumi ; Kim, S.H. ; Suzuki, Ryo ; Lee, Sang-Rim ; Iida, Ryo ; Hoshii, Takuya ; Jevasuwan, W. ; Maeda, T. ; Yasuda, Toshiyuki ; Ichikawa, Osamu ; Fukuhara, N. ; Hata, Masaharu ; Takenaka, Mitsuru ; Takagi, Shinichi
Author_Institution
Univ. of Tokyo, Tokyo, Japan
Volume
13
Issue
4
fYear
2013
fDate
Dec. 2013
Firstpage
456
Lastpage
462
Abstract
We have quantitatively evaluated the interface trap density inside the conduction band (CB) of InxGa1-xAs metal-oxide-semiconductor (MOS) structures and have systematically investigated the impact of the interface traps inside the CB on the inversion-layer mobility in InxGa1-xAs MOS field-effect transistors with various interface structures. Furthermore, we have tried to clarify the physical origin of the interface traps inside the CB. It was found that a large number of interface traps are distributed inside the CB of InxGa1-xAs inducing Fermi level pinning (FLP), the energy level of which is tunable by changing the InxGa1-xAs MOS interface structures. Furthermore, it was clarified that FLP inside the CB degrades the mobility in the high inversion carrier concentration region. We also found from the obtained results and reported theoretical results that a possible physical origin of the interface traps inside the CB is As-As dimers formed at the interfaces.
Keywords
Fermi level; III-V semiconductors; MOSFET; carrier density; conduction bands; gallium arsenide; indium compounds; interface states; inversion layers; Fermi level pinning; InGaAs; MOS field-effect transistor; MOS interface structure; conduction band; energy level; high inversion carrier concentration region; interface trap density; inversion layer mobility; metal-oxide-semiconductor field effect transistor; Aluminum oxide; Capacitance-voltage characteristics; Energy states; Indium; Indium gallium arsenide; Logic gates; MOSFET; Fermi level pinning; InGaAs; conduction band; interface trap;
fLanguage
English
Journal_Title
Device and Materials Reliability, IEEE Transactions on
Publisher
ieee
ISSN
1530-4388
Type
jour
DOI
10.1109/TDMR.2013.2289330
Filename
6656906
Link To Document