Resolution of a current-mode algorithmic analog-to-digital converter

Author

Giustolisi, G. ; Palumbo, G. ; Pennisi, S.

Author_Institution

Dipt. Elettrico Elettronico e Sistemistico, Catania Univ., Italy

Volume

49

Issue

10

fYear

2002

fDate

10/1/2002 12:00:00 AM

Firstpage

1480

Lastpage

1486

Abstract

Errors limiting the resolution of current-mode algorithmic analog-to-digital converters are mainly related to current mirror operation. While systematic errors can be minimized by proper circuit techniques, random sources are unavoidable. In this paper a statistical analysis of the resolution of a typical converter is carried out taking into account process tolerances. To support the analysis, a 4-bit ADC, realized in a 0.35-μm CMOS technology, was exhaustively simulated. Results were found to be in excellent agreement with theoretical derivations.

Keywords

CMOS integrated circuits; analogue-digital conversion; current-mode circuits; error analysis; network analysis; statistical analysis; tolerance analysis; 0.35 micron; 4 bit; A/D converters; CMOS technology; algorithmic ADC; analog-to-digital converters; circuit analysis; circuit techniques; current-mode ADC; error analysis; resolution; statistical analysis; tolerance analysis; Analog integrated circuits; Analog-digital conversion; Broadband amplifiers; CMOS technology; Circuit topology; Integrated circuit technology; Mirrors; Optical amplifiers; Optical feedback; Solid state circuits;

fLanguage

English

Journal_Title

Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on

Publisher

ieee

ISSN

1057-7122

Type

jour

DOI

10.1109/TCSI.2002.803353

Filename

1039500