DocumentCode
83605
Title
Interactions Between Line Edge Roughness and Random Dopant Fluctuation in Nonplanar Field-Effect Transistor Variability
Author
Leung, Greg ; Chi On Chui
Author_Institution
Dept. of Electr. Eng., Univ. of California at Los Angeles, Los Angeles, CA, USA
Volume
60
Issue
10
fYear
2013
fDate
Oct. 2013
Firstpage
3277
Lastpage
3284
Abstract
Investigations on device variability for three different emerging field-effect transistor (FET) technologies are performed to determine the statistical dependence or independence of line edge roughness (LER) and random dopant fluctuation (RDF) variability mechanisms. The device candidates include standard inversion-mode (IM) FinFETs, junctionless (JL) FinFETs, and tunnel FETs (TFETs) designed for sub-32-nm generations. Using technology computer-aided design simulations, extracted standard deviations in linear and saturation threshold voltages ( VT,lin and (VT,sat), ON-state current (ION), OFF-state current (IOFF), subthreshold swing (SS), and drain-induced barrier lowering (DIBL) are compared for the cases: 1) when LER and RDF are separately modeled during device simulations and assumed to combine in an uncorrelated fashion, and 2) when LER and RDF are simultaneously modeled in device simulations and no assumption is made about their interaction. After performing the comparisons for each FET technology, we find that LER and RDF cannot be considered independent for IM-FinFETs and TFETs, but can be for JL-FinFETs. The different outcomes are related to local versus distributed variability dependencies in each transistor type. Our conclusions reinforce the need for more comprehensive treatment of variability effects to provide accurate estimations of expected device variability in junction-based FETs.
Keywords
MOSFET; electronic engineering computing; technology CAD (electronics); DIBL; FET technology; IM FinFET; JL FinFET; LER; OFF-state current; ON-state current; RDF; SS; TFET; device simulations; device variability; distributed variability dependency; drain-induced barrier lowering; inversion-mode FinFET; junctionless FinFET; line edge roughness; linear threshold voltages; nonplanar field-effect transistor variability; random dopant fluctuation variability mechanism; saturation threshold voltages; statistical dependence; subthreshold swing; technology computer-aided design simulations; tunnel FET; FinFETs; Logic gates; Predictive models; Resistors; Resource description framework; FinFET; junctionless; line edge roughness (LER); random dopant fluctuation (RDF); tunnel FET (TFET); variability;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/TED.2013.2276072
Filename
6579670
Link To Document