Dual multiple-polynomial LFSR for low-power mixed-mode BIST

Mixed-mode BIST offers complete fault coverage with short test application times and small test data requirements. Reducing power dissipation during testing is becoming necessary for decreasing the risks of reliability problems and manufacturing yield loss. Several techniques have been recently proposed for reducing power dissipation during BIST. The work presented addresses the problem of reducing power dissipation in mixed-mode BIST. A new mixed-mode test pattern generator is proposed with reduced power dissipation during test when compared with existing test pattern generators. This is achieved by combining the masking properties of AND/OR composition with LFSR reseeding. Extensive experiments were performed on several benchmark circuits using commercial synthesis and simulation tools to validate the efficiency and assess the overhead of the proposed solution. Experimental results show that reductions up to 20% in average power dissipation during test can be achieved when compared with traditional test pattern generators.