Contention-Free Interleavers for High-Throughput Turbo Decoding

This paper presents a low-complexity interleaver design that facilitates the high throughput turbo decoding required for next generation wireless systems. Specifically, it addresses the interleaver design issues that arise when several Log-MAP processors are used in parallel to improve turbo decoding throughput. In such a parallel decoder, memory access contentions occur when more than one extrinsic value is to be written to or read from the same memory block at the same time. These contentions may be avoided by designing contention- free (CF) interleavers that incorporate hardware constraints into the interleaver description. The paper first derives bounds on the number of CF interleavers, demonstrating that the fraction of interleavers of a given size that are contention-free is quite small. In spite of this, a class of contention-free "inter-window shuffle" (IWS) interleavers are shown via simulation to achieve near-WCDMA performance. Further, the paper shows that the memory requirement of CF IWS interleavers is small compared to an alternate contention-resolving method that uses a modified memory addressing scheme. Finally, we note that the advantages of contention-free interleavers have led to the adoption of a CF quadratic permutation polynomial (QPP) interleaver in the 3 GPP long term evolution (LTE) standard.