• DocumentCode
    83683
  • Title

    Processor-Based Strong Physical Unclonable Functions With Aging-Based Response Tuning

  • Author

    Joonho Kong ; Koushanfar, Farinaz

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA
  • Volume
    2
  • Issue
    1
  • fYear
    2014
  • fDate
    Mar-14
  • Firstpage
    16
  • Lastpage
    29
  • Abstract
    A strong physically unclonable function (PUF) is a circuit structure that extracts an exponential number of unique chip signatures from a bounded number of circuit components. The strong PUF unique signatures can enable a variety of low-overhead security and intellectual property protection protocols applicable to several computing platforms. This paper proposes a novel lightweight (low overhead) strong PUF based on the timings of a classic processor architecture. A small amount of circuitry is added to the processor for on-the-fly extraction of the unique timing signatures. To achieve desirable strong PUF properties, we develop an algorithm that leverages intentional post-silicon aging to tune the inter- and intra-chip signatures variation. Our evaluation results show that the new PUF meets the desirable inter- and intra-chip strong PUF characteristics, whereas its overhead is much lower than the existing strong PUFs. For the processors implemented in 45 nm technology, the average inter-chip Hamming distance for 32-bit responses is increased by 16.1% after applying our post-silicon tuning method; the aging algorithm also decreases the average intra-chip Hamming distance by 98.1% (for 32-bit responses).
  • Keywords
    computer architecture; cryptographic protocols; digital signatures; microprocessor chips; Hamming distance; PUF; aging based response tuning; circuit components; circuit structure; computing platforms; exponential number; intellectual property protection protocols; processor architecture; processor based strong physical unclonable functions; unique chip signatures; Aging; Circuit optimization; Delays; Logic gates; Microprocessors; Multicore processing; Network security; Silicon; Temperature measurement; Circuit aging; Multi-core processor; Negative bias temperature instability; Physically unclonable function; Post-silicon tuning; Secure computing platform; circuit aging; multi-core processor; negative bias temperature instability; postsilicon tuning; secure computing platform;
  • fLanguage
    English
  • Journal_Title
    Emerging Topics in Computing, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    2168-6750
  • Type

    jour

  • DOI
    10.1109/TETC.2013.2289385
  • Filename
    6656920