A parallel algorithm for channel routing problems [VLSI]

A parallel algorithm for channel routing problems is presented. The problem is to route the given interconnections between two rows of terminals on a multilayer channel where the channel area must be minimized. The current advancement of VLSI chip technology allows one to use four layers composed of two metal layers and two polysilicon layers for routing in a chip. The goal of the proposed parallel algorithm is to find the near-optimum routing solution for the given interconnections in a short time. The algorithm is applied to four-layer channel routing problems requiring n×m×2 processing elements for the n-net-m-track problem. The algorithm has three advantages over the conventional algorithms: (1) it can be easily modified for accommodating more than four-layer problems; (2) it runs both on a sequential machine and on a parallel machine with maximally n×m×2 processors; and (3) the program size is very small. The algorithm is verified by solving seven bench-mark problems