An SFS Berger check prediction ALU and its application to self-checking processor designs

Author

Lo, Jien-Chung ; Thanawastien, Suchai ; Rao, T.R.N. ; Nicolaidis, Michael

Author_Institution

Dept. of Electr. Eng., Rhode Island Univ., Kingston, RI, USA

Volume

11

Issue

4

fYear

1992

fDate

4/1/1992 12:00:00 AM

Firstpage

525

Lastpage

540

Abstract

A strongly fault secure (SFS) ALU design based on the Berger check prediction (BCP) technique is presented. The fault and error models of a large class of VLSI ALU designs are discussed. The proposed design is proved to be fault-secure and self-testing with respect to any single fault in the ALU part. The proposed BCP ALU is proved to be SFS with any design of BCP circuit. Consequently, a self-checking processor whose data path is encoded entirely in a Berger code can be achieved. An efficient self-checking processor can then be designed

Keywords

VLSI; automatic testing; built-in self test; circuit CAD; error detection; fault tolerant computing; logic CAD; logic testing; BIST; Berger check prediction; Berger code; VLSI ALU; error models; fault models; self-checking processor designs; self-testing; strongly fault secure; Built-in self-test; Business continuity; Circuit faults; Computer errors; Costs; Error correction; Hardware; Process design; Registers; Very large scale integration;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.125100

Filename

125100