DocumentCode
837658
Title
CMOS Integration of Dual Work Function Phase-Controlled Ni Fully Silicided Gates (NMOS:NiSi, PMOS: 
, and  phase-controlled Ni fully silicided (FUSI) gates on HfSiON was investigated. For the first time, the integration of NiSi FUSI gates on n-channel MOS (NMOS) and Ni<sub>31</sub>Si<sub>12</sub> FUSI gates on p-channel MOS (PMOS) with good V<sub>t</sub> control to short gate lengths (L<sub>G</sub>=50 nm, linear V<sub>t</sub> of 0.49 V for NMOS, and -0.37 V for PMOS) is demonstrated. A poly-Si etch-back step was used to reduce the poly-Si height on PMOS devices, allowing for the linewidth-independent formation of NiSi on NMOS and Ni-rich silicides on PMOS with a two-step rapid thermal processing (RTP) silicidation process. The process space for the scalable formation of NiSi on NMOS and Ni<sub>2</sub>Si or Ni<sub>31 </sub>Si<sub>12</sub> on PMOS devices was investigated. It was found that within the process window for linewidth-independent NiSi FUSI formation on 100-nm poly-Si NMOS devices, it is possible to control the silicide formation on PMOS devices by adjusting the poly-Si etch-back and RTP1 conditions to obtain either Ni<sub>2</sub>Si or Ni<sub>31</sub>Si<sub>12</sub> FUSI gates. A reduction in the PMOS threshold voltage of 90 mV and improved device performance (18% I<sub>on </sub> improvement at I<sub>off</sub>=100 nA/mum) was obtained for Ni <sub>31</sub>Si<sub>12</sub> compared to Ni<sub>2</sub>Si FUSI gates, as well as a V<sub>t</sub> reduction of 350 mV when compared to a single WF flow using NiSi FUSI gates on PMOS</div></div>
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<div class='row g-0 align-items-center mb-2'><div class='col-12 col-md-3 fullRecLabelEnglish fw-bold mb-2 mb-md-0'><span class='text-muted small'>Keywords</span></div><div class='col-12 col-md-9 leftDirection leftAlign'>CMOS integrated circuits; MOSFET; etching; hafnium compounds; high-k dielectric thin films; nickel alloys; rapid thermal processing; silicon alloys; silicon compounds; work function; -0.37 V; 0.49 V; 100 nm; 50 nm; CMOS integration; FUSI gates; NMOS:NiSi; NiSi-HfSiON; PMOS threshold voltage; PMOS:Ni<sub>2</sub>Si; PMOS:Ni<sub>31</sub>Si<sub>12</sub>; dual work function; high-k dielectric; linewidth-independent formation; n-channel MOS; p-channel MOS; phase-controlled Ni fully silicided gates; poly-Si etch-back step; rapid thermal processing silicidation process; silicide formation; CMOS process; CMOS technology; Etching; High-K gate dielectrics; MOS devices; Rapid thermal processing; Silicidation; Silicides; Temperature; Threshold voltage; <formula formulatype=)
$hbox{Ni}_{2}hbox{Si}$ ; $hbox{Ni}_{31}hbox{Si}_{12}$ $k$
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/LED.2006.886414
Filename
4016191
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