DocumentCode :
837774
Title :
Analysis of Poly-Si TFT Degradation Under Gate Pulse Stress Using the Slicing Model
Author :
Tai, Ya-Hsiang ; Huang, Shih-Che ; Chen, Chien-Kwen
Author_Institution :
Dept. of Photonics, Nat. Chiao Tung Univ., Hsinchu
Volume :
27
Issue :
12
fYear :
2006
Firstpage :
981
Lastpage :
983
Abstract :
The device degradation of polycrystalline-silicon thin-film transistors stressed with different gate pulse waveforms is investigated. It is first observed that the degradation is dependent on the rising time of the gate pulses for the gate voltage swing below the threshold voltage. The degradation ratio of the mobility is analyzed with respect to two factors, namely, the magnitude of the lateral transient electric field and the change in the numbers of the carrier near the edges of the channel. A new index considering these two factors is proposed to depict the device degradation. It shows good linearity between the degradation in mobility and the proposed index
Keywords :
carrier mobility; elemental semiconductors; semiconductor device models; semiconductor device reliability; semiconductor device testing; silicon; thin film transistors; AC stress; dynamic stress; gate pulse stress; gate pulse waveforms; gate voltage swing; lateral transient electric field; mobility degradation; poly-Si TFT degradation; polycrystalline-silicon thin-film transistors; slicing model; threshold voltage; Degradation; Displays; Electrodes; Fabrication; Glass; Silicon compounds; Stress; Substrates; Thin film transistors; Threshold voltage; AC stress; dynamic stress; poly-Si thin-film transistors (TFTs); reliability;
fLanguage :
English
Journal_Title :
Electron Device Letters, IEEE
Publisher :
ieee
ISSN :
0741-3106
Type :
jour
DOI :
10.1109/LED.2006.886416
Filename :
4016202
Link To Document :
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