Author :
Liu, Chang-Ming ; Lee, Chang-Chun ; Chiang, Kuo-Ning
Abstract :
During the design and manufacturing processes of electronic packaging, solder joints are fabricated using a variety of methods to provide both mechanical and electrical connections for different applications. They include flip chip, wafer level chip scale packaging (WLCSP), fine pitch ball grid array (BGA), and chip scale packaging (CSP). The solder joint shape prediction methods have been incorporated as a design tool to enhance the reliability of the WLCSP. However, the reliability of solder joints for a large chip size such as 10mmtimes10mm without underfill remains questionable. In this research, a hybrid method combining an analytical algorithm with the energy-based approach is applied to predict standoff heights and geometry profiles of the solder joints. In addition, a hybrid-pad-shape system is proposed to design the solder ball layout, and to enhance the reliability of the solder joints. Next, a nonlinear and parametric finite element analysis is conducted to investigate the reliability issues that result from several design parameters. In addition, an experimental validation is completed to verify the correctness and feasibility of the solder joint shape prediction methods and finite element analysis procedures. The design parameters considered in this study include solder joint layout, solder volume, pad diameter, as well as the ratio and orientation of the elliptical pad. With regards to solder joint layout design, the solder joints located in the corner areas can be considered as structural dummy balls with no electrical signals passing through them. The results reveal that when the WLCSP has large round pads, or properly oriented elliptical solder joint pads at the corner areas underneath the chip, then the maximum equivalent plastic strain of the solder joints will be effectively reduced. As a result, the solder joint fatigue life under thermal loading will be greatly enhanced. Furthermore, the findings of this research can be used as a design guideli- - ne for electronic packaging with area array interconnections such as CSP, flip chip packaging, Super CSP, and fine pitch BGA
Keywords :
chip scale packaging; filler metals; finite element analysis; integrated circuit layout; reliability; solders; analytical algorithm; area array interconnections; chip scale packaging; design guideline; design process; electrical connections; electronic packaging; elliptical pad; energy-based approach; equivalent plastic strain; fatigue life; fine pitch BGA; fine pitch ball grid array; finite element analysis; flip chip packaging; hybrid method; hybrid pad shape; manufacturing process; mechanical connection; solder ball layout; solder joint reliability; solder joint shape prediction; solder joints geometry profiles; solder joints layout design; solder joints standoff heights; structural dummy balls; thermal loading; wafer level packaging; Chip scale packaging; Electronic packaging thermal management; Electronics packaging; Finite element methods; Flip chip; Prediction methods; Process design; Shape; Soldering; Wafer scale integration; Elliptical pad; hybrid method; hybrid-pad-shape (HPS); nonlinear finite element analysis; solder joint reliability; wafer level chip scale packaging (WLCSP);
