Modelling and test generation for MOS transmission gate stuck-open faults

Author

Belkadi, M. ; Mouftah, H.T.

Author_Institution

Dept. of Electr. Eng., Queens Univ., Kingston, Ont., Canada

Volume

139

Issue

1

fYear

1992

fDate

2/1/1992 12:00:00 AM

Firstpage

17

Lastpage

22

Abstract

The authors present a testable design for a MOS transmission gate (whether it is a pass transistor or a CMOS transmission gate) when it is isolated (i.e. it does not have transmission gate neighbours nor does it feed a bus) and subject to a stuck-open fault condition in a given CMOS VLSI circuit. The proposed design consists of the original transmission gate to which a MOS transistor is added, so that the high impedance state resulting from a stuck-open fault condition can be eliminated. It is shown that the new approach can be extended to MOS transmission gate-based multiplexers for which a better testing scheme is ensured. It is also demonstrated that not all transmission gates need to be augmented by using an additional MOS transistor, so that the circuit under study can be kept combinational while in the test mode. Finally, the test generation for isolated transmission gates in the context of the PODEM algorithm is discussed

Keywords

CMOS integrated circuits; MOS integrated circuits; VLSI; automatic testing; fault location; integrated circuit testing; integrated logic circuits; logic gates; logic testing; semiconductor device models; CMOS VLSI circuit; MOS transmission gate; PODEM algorithm; high impedance state; logic circuits; multiplexers; pass transistor; stuck-open faults; test generation; testable design;

fLanguage

English

Journal_Title

Circuits, Devices and Systems, IEE Proceedings G

Publisher

iet

ISSN

0956-3768

Type

jour

Filename

125111