Low power receiver architectures for multi-carrier CDMA

The implementation of multi-carrier code division multiple access (MC-CDMA) receivers in digital hardware is considered. A low power algorithm is proposed which treats the received signal as a block of symbols, rather than processing the symbols individually. This reduces power by holding one input to the multiplier circuits used in the multi-carrier combiner multiplication constant for a number of clock cycles. This produces a 50% reduction in power consumption for a multi-user detection combiner circuit. This algorithm is also extended to the fast Fourier transform (FFT) block and allows an overall power drain reduction of 13% for the whole receiver. A software configurable version of the circuit, which allows a trade-off between power reduction and processing delay, is also described