Title :
Calculating the effective pattern rate for high-speed board test applications
Author_Institution :
Teradyne Inc., Boston, MA, USA
fDate :
5/1/1989 12:00:00 AM
Abstract :
A complex interplay of tester specifications can force in-circuit and functional board test systems to operate at less than their specified maximum pattern rates in real-world test applications. The author explores the factors that combine to limit test speed. He develops models for calculating the effective pattern rate based on tester performance data and the characteristics of the VLSI board under test
Keywords :
VLSI; automatic test equipment; printed circuit testing; VLSI board; effective pattern rate; functional board test systems; high-speed board test applications; in-circuit test system; Circuit testing; Clocks; Detectors; Fixtures; Floors; Logic testing; Propagation delay; System testing; Timing; Very large scale integration;
Journal_Title :
Industrial Electronics, IEEE Transactions on
