Analogy between VLSI floorplanning problems and realisation of a resistive network

The problem of minimising the area of a rectangular VLSI chip by a proper choice of dimensions of the rectangular blocks forming the chip is discussed. The layout of the chip is defined by its floorplan with the areas of the building blocks given a priori. An analogy is used which exists between this problem and the problem of designing a resistive network with a given topology. In such an analogy, the area of a block or the whole chip corresponds to the power absorbed in a resistor or the whole network, respectively. Since the total power absorbed by the network is equal to the sum of the power absorbed by the resistors, the network model inherently corresponds to a chip design with zero wasted area. Thus, in terms of the network realisation concepts, the problem reduces to finding assignment of resistor values to a network with a given topology such that the power absorbed in each of the resistors is given a priori. A step-by-step procedure is presented which shows a way to reach an approximate solution in a finite number of steps