Automated synthesis for testability

The authors present an integrated, compiler-driven approach to digital chip design that automates mask layout and test-pattern generation for 100% stuck-at fault coverage. This approach is well suited for designs where it is most important the minimize the design cycle time rather than the silicon area. The authors show that by compiling from a unified design specification followed by logic synthesis it is possible to reduce the problem of automatic test-pattern generation. They present a language-based design capture and logic synthesis with hierarchical test pattern generation and redundancy removal techniques. A section on benchmark results highlights the close coupling of a language-based design specification, logic synthesis, and testability.<>