Numerical simulation of parasitic resistance effects in polycrystalline silicon TFTs

Parasitic resistance effects have been investigated in n-channel polycrystalline (polysilicon) silicon thin film transistors (TFTs). We show, both experimentally, and by using two-dimensional numerical simulations, that the transfer characteristics and, in particular, the transconductance are degraded by parasitic resistance effects, which are related to residual implant damage. In particular, we show that residual implant damage gives rise to two types of defected regions across the edges of the gate: the first, not overlapped by the gate, which mainly controls the parasitic resistance. The second, which is gate overlapped, can affect the behavior of the threshold voltage by modifying the classical short channel effect to the reverse short channel effect. The analysis demonstrates that for the fabrication of short-channel polysilicon TFTs an exact control of the implant-damaged regions is necessary.