Title :
FRAM design style utilising bit-plate parallel cell architecture
Author_Institution :
Sch. of Electron. & Electr. Eng., Kyungpook Nat. Univ., Daegu, South Korea
Abstract :
A new FRAM (ferroelectric RAM) design method, utilising a bit-plate parallel cell architecture is presented. This method is effective in reducing circuit and layout overhead caused by the on-pitch plate control circuitry. It also reduces the power consumption in the memory array. Implementation results for a 0.13 μm CMOS technology, 512 kb FRAM prototype show that the memory block area in the proposed architecture is 15.6% less than that of a conventional structure.
Keywords :
CMOS memory circuits; SRAM chips; ferroelectric storage; integrated circuit design; low-power electronics; 0.13 micron; 512 kbit; FRAM bit-plate parallel cell architecture; cell capacitor plate; ferroelectric storage integrated CMOS technology; memory array; memory block area; nonvolatile memory; on-pitch plate control circuitry; power consumption reduction;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20031104
